In semiconductor device fabrication processes it is generally desirable to minimize the total number of steps in the process. Furthermore, it is generally desirable to allow the greatest latitude in fabrication process parameters while still yielding satisfactory semiconductor device characteristics. Stated differently, the simpler and the more robust the process the better suited it is for large scale manufacturing of semiconductor devices and the greater the number of devices which can be manufactured.
One of the semiconductor device characteristics which is of concern for most device types (e.g., microprocessors, memory devices, etc.), is the resistance of the interface between the active regions (source, drain, etc.) of the device and the contacts or interconnects (metalization lines, etc.) to other devices. The greater the resistance at this interface the more power that is required to operate the device, the greater the heat generated and the slower the device operation. Therefore, it is generally desirable to have the interface resistivity be as low as possible.
One commonly known prior art fabrication process (explained further below) used to minimize the interface resistivity requires multiple steps and relatively tight fabrication process parameters in order to yield satisfactory resistivity values. In contrast, the present invention reduces the number of steps as compared to the prior art and allows greater fabrication parameter variation while yielding equivalent, or even improved, semiconductor device films with lower interface resistivity values as compared to the prior art.